For example, the technique known in Japanese Patent Laid-Open Publication Heisei 9-231164 is per se known. In this prior art of the publication, a CPU is connected to a high speed bus and a low speed I/O device is connected to a low speed bus, and a bus bridge is connected between the two buses. When the CPU is to read data from the low speed I/O device, it writes the address of the low speed I/O device in which this data is stored to the bus bridge, and the bus bridge reads out the data in the address which has been written from the CPU from the low speed I/O device and stores it. By doing this, the data which the CPU wishes to read is pre-fetched to the bus bridge. The CPU is able to acquire data from the low speed I/O device by reading in the pre-fetched data in the bus bridge from the bus bridge.